Semiconductor storage device and method for manufacturing the same

ABSTRACT

A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims benefit of priority from theJapanese Patent Application No. 2008-52185, filed on Mar. 3, 2008, theentire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The invention relates to a semiconductor storage device and a method formanufacturing the same.

In conventional non-volatile semiconductor storage devices, regionsbetween word lines that have a layer structure including a tunnel oxidefilm, a floating gate electrode, an interpoly insulating film, and acontrol gate electrode are filled using an oxide film or a nitride film.However, as devices have shrunk to microscopic sizes, various problemshave arisen. One problem is that because the interval between the wordlines has been reduced, variation among threshold voltages of thefloating gate electrodes has increased due to parasitic capacitancesgenerated between the floating gate electrodes of adjacent word lines,and writing speed has dropped due to parasitic capacitances generatedbetween the floating gates and diffusion layer. Another problem is thatthe material embedded between the electrodes breaks down as a result ofthe large electric field applied between the electrodes.

One proposed solution for such problems is to provide air gaps (spaces)between the word lines to reduce the parasitic capacitances therebysuppress the variation in the threshold voltages of the floating gateelectrodes and the reduction in the writing speed.

A known method for forming air gaps is to use an organic material as asacrificial film and remove the sacrificial film by ashing (see, forexample, Japanese Patent Laid-Open No. 1-137651). However, when such amethod is applied to form the air gap between the word lines, there is aproblem that the carbon or the like included in the organic materialdegrades the tunnel oxide film.

A further known method of forming the air gaps is to form a spacer madeup of a silicon nitride film to cover the word line, form a sacrificialfilm made up of a silicon oxide film up to a predetermined heightbetween the word lines, form a mini-spacer made up of a silicon nitridefilm on the sacrificial film, and remove the sacrificial film whilepreserving a selection ratio between the sacrificial film and thesilicon nitride film (see, for example, Daewoong Kang et al, The AirSpacer Technology for Improving the Cell Distribution in 1 Giga Bit NANDFlash Memory, IEEE NVSMW2006, p 36-p 37).

However, this method has a problem in that hot carriers are generatedwhen a silicon nitride film is used as a spacer. A further problem isthat hydrogen included in the silicon nitride film during the heatingprocess causes degradation of the tunnel oxide film.

Thus, conventional methods for forming the air gap have a problem inthat the tunnel oxide film is degraded, causing a drop in thereliability of the semiconductor storage device.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided asemiconductor storage device comprising:

a semiconductor substrate;

a plurality of word lines formed with a predetermined interval on thesemiconductor substrate;

a selection transistor provided at an end portion of the plurality ofword lines;

a first insulating film formed so as to cover side surfaces of the wordlines, a side surface of the selection transistor, and a surface of thesemiconductor substrate between the word lines;

a high-permittivity film formed on the first insulation film, thehigh-permittivity film including a metal oxide and having a higherpermittivity than the first insulating film;

a second insulating film formed so as to cover the upper surface of theword lines and the selection transistor;

a first air-gap portion located between the word lines and surrounded bythe high-permittivity film and the second insulating film; and

a second air-gap portion formed via the first insulating film and thehigh-permittivity film at a sidewall portion, which opposes theselection transistor, of the word line adjacent to the selectiontransistor, an upper portion of the second air-gap portion being coveredby the second insulating film.

According to one aspect of the present invention, there is provided asemiconductor storage device manufacturing method comprising:

forming on a semiconductor substrate a plurality of word lines separatedby a predetermined interval, each including a first insulating film, acharge storing layer, a second insulating film and a control gateelectrode layered in the stated order, and a selection transistor ateach end of each of the plurality of word lines at a location adjacentto a plurality of memory regions;

forming a first oxide film so as to cover the word lines, the selectiontransistors and the semiconductor substrate;

forming, on the first oxide film, a high-permittivity film whichincludes a metal oxide and has a higher permittivity than the firstoxide film;

forming a second oxide film on the high-permittivity film so as to beembedded in gaps between the word lines;

removing the second oxide film, the high-permittivity film and the firstoxide film so as to expose a surface of the semiconductor substratebetween adjacent selection transistors and a surface of thesemiconductor substrate between the selection transistors and the wordlines adjacent to the selection transistors, and forming a sidewallfilms made up of the first oxide film, the high-permittivity film andthe second oxide film on sidewall portions of the selection transistorsand on sidewall portions which are of the word lines adjacent to theselection transistors and oppose the selection transistors;

forming a nitride film so as to cover the sidewall films and thesemiconductor substrate;

forming a third oxide film so as to be embedded between the selectiontransistors and between the selection transistors and the word lineadjacent to the selection transistors;

removing the third oxide film and the nitride film so as to expose uppersurfaces of the control gate electrodes and an upper surface of thesecond oxide film;

removing the second oxide film; and

forming a fourth oxide film so as to cover an upper portion of regionsfrom which the second oxide film has been removed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view for explaining a manufacturing methodof a semiconductor storage device according to an embodiment of theinvention;

FIG. 2 is a cross-sectional view showing a step subsequent to FIG. 1;

FIG. 3 is a cross-sectional view showing a step subsequent to FIG. 2;

FIG. 4 is a cross-sectional view showing a step subsequent to FIG. 3;

FIG. 5 is a cross-sectional view showing a step subsequent to FIG. 4;

FIG. 6 is a cross-sectional view showing a step subsequent to FIG. 5;

FIG. 7 is a cross-sectional view showing a step subsequent to FIG. 6;

FIG. 8 is a cross-sectional view showing a step subsequent to FIG. 7;

FIG. 9 is a view showing the gap between word lines which areapproximated as parallel plates;

FIG. 10 is a process cross-sectional view for explaining a manufacturingmethod of a semiconductor storage device according to a modification;

FIG. 11 is a cross-sectional view showing a step subsequent to FIG. 10;

FIG. 12 is a schematic view of the semiconductor storage deviceaccording to a modification; and

FIG. 13 is a schematic view of the semiconductor storage deviceaccording to the modification.

DESCRIPTION OF THE EMBODIMENTS

The following describes embodiments of the invention with reference tothe drawings.

FIGS. 1 to 8 are process cross-sectional drawings for explaining amanufacturing method of a semiconductor storage device according to anembodiment of the invention. In the drawings (a) is a verticalcross-section of a memory cell array portion taken along a bit line and(b) is a vertical cross-section of an end portion of the memory cellarray and selection gate transistor, taken along a bit line.

As shown in FIG. 1, a tunnel oxide film 2 made up of a silicon oxidefilm and a floating gate electrode 3 formed from a polysilicon film areformed on a semiconductor substrate 1.

The floating gate electrode 3, the tunnel oxide film 2, and thesemiconductor substrate 1 are then removed at a predetermined intervalin a first direction (bit line direction) to form grooves. A siliconoxide film of a predetermined height is embedded in the grooves to formdevice separation regions (not shown).

The interpoly insulating film 4 is then formed so as to cover thefloating gate electrodes 3 and the device separation regions, and afirst polysilicon film is formed on the interpoly insulating film 4.Portions of the first polysilicon film and the interpoly insulating film4 in regions which are to be formed into selection transistors ST andperipheral transistors (not shown in the drawings) are removed to formgrooves. A second polysilicon film is formed on the first polysiliconfilm so as to be embedded in the grooves.

In the memory cell array portion, a control gate electrode 5 is made upof the first polysilicon film and the second polysilicon film. Further,the selection transistors ST and the peripheral transistors have anetching interpoly structure in which the polysilicon film (electrodefilm) above and below the interpoly insulating film 4 are connected.

A silicon nitride film 6 is then formed on the control gate electrode 5.Next, the word lines WL and the selection transistors ST are fabricatedby removing, with a predetermined interval in a second direction (wordline direction) perpendicular to the first direction, the siliconnitride film 6, the control gate electrode 5, the interpoly insulatingfilm 4, the floating gate electrode 3 and the tunnel oxide film 2. Aselection transistor ST is provided at each end of each of the pluralityof word lines WL.

As shown in FIG. 2, a silicon oxide film 11 is formed so as to cover theword lines WL, the selection transistors ST, and the semiconductorsubstrate 1 using a CVD (Chemical Vapor Deposition) method. The siliconoxide film 11 is formed using a high temperature (e.g. 750° C. or more).After formation, the silicon oxide film 11 is heat treated(densification processing) at high temperature for a predeterminedperiod. According to this process, the silicon oxide film 11 becomes ahigh-density film. The densification processing may be performed in aconventional oven or by RTA (Rapid Thermal Annealing).

Diffusion layers (not shown in the drawings) are then formed byimplanting arsenic or the like in surface portions of the semiconductorsubstrate 1 between the word lines WL, between the selection transistorsST, and between the selection transistors ST and a word line WL1adjacent to the selection transistors ST.

A high-permittivity film 12, which has a higher permittivity than thesilicon oxide film 11, is formed on the silicon oxide film 11 by ALD(Atomic Layer Deposition) method. Examples of materials which can beused as the high-permittivity film 12 include metal oxides including Zroxides such as ZrO₂, PbZrO₂, BaZrO₃, Hf oxides such as HfO₂, HfON, andHfAlO, La oxides such as LaO₃, Al oxides such as Al₂O₃ and AlZrO₅, Taoxides such as Ta₂O₅, Ti oxides such as TiO₂ and Y oxides such as Y₂O₃.

Next, a sacrificial film 13 made up of a silicon oxide film is formed bya CVD method so as to be embedded between the word lines WL on thehigh-permittivity film 12. The sacrificial film 13 is formed into a filmat lower temperature (e.g. 650° C. or less) than the temperature atwhich the silicon oxide film 11 is formed. Consequently, the sacrificialfilm 13 has a lower density than the silicon oxide film 11.

As shown in FIG. 3, etch-back is performed using RIE (Reactive IonEtching) to expose the surface of the semiconductor substrate 1 betweenthe selection transistors ST and between the selection transistors STand the word line WL1 adjacent to the selection transistors ST, and thesacrificial film 13, the high-permittivity film 12, and the siliconoxide film 11 are removed.

As a result, sidewalls (sidewall films) SW made up of the sacrificialfilm 13, the high-permittivity film 12 and the silicon oxide film 11 areformed on sidewall portions of the selection transistors ST and theselection transistor ST side of the word line WL1. A high-concentrationdiffusion layer (not shown in the drawings) is formed in surfaceportions of the semiconductor substrate 1 between the selectiontransistors ST by masking the sidewalls SW and implanting arsenic or thelike to form an LDD (Lightly Doped Drain) structure.

As shown in FIG. 4, a silicon nitride film 15 is formed by an ALD methodso as to cover the word lines WL, the selection transistors ST, thesidewalls SW and the semiconductor substrate 1.

Then, a silicon oxide film 16 is formed so as to be embedded between theselection transistors ST and between the selection transistors and theword lines WL1 using a high-density plasma CVD technique which allows aselection ratio of approximately “2” with respect to the sacrificialfilm 13 to be obtained. As a consequence of using the high-densityplasma CVD technique, the silicon oxide film 16 is of a higher densitythan the sacrificial film 13.

Next, the flattening by CMP (Chemical Mechanical Polishing) is performedwith the silicon nitride film 6 as a stopper.

The silicon nitride film 6 is then removed by CDE (Chemical Dry Etching)to expose an upper surface of the control gate electrode 5 as shown inFIG. 5. When the silicon nitride film 6 is removed, a certain amount ofthe silicon oxide film 16, the silicon nitride film 15 and the like arealso removed. At this point, the upper surface of the sacrificial film13 is exposed.

As shown in FIG. 6, a portion or all of the control gate electrodes 5are formed from a silicide 17. The silicide metal material can be atransition metal from groups 4 through 11, such as Ni, Ti, Co, Pt, Pd,Ta or Mo.

Next, a resist film 18 is formed, the selection transistors ST arecovered, lithography is performed to form openings in the memory cellarray portion, and pattering is performed.

As shown in FIG. 7, the sacrificial film 13 between the word lines WLand the sacrificial film 13 of the sidewall portion on the selectiontransistor ST side of the word line WL1 are removed by etching for whicha selection ratio with respect to the high-permittivity film 12 can beobtained. For instance, a selection ratio between the sacrificial film13 and the high-permittivity film 12 can be obtained using wet etchingwith a fluoric acid chemical solution such as BHF (ammonium fluoride:NH₄F/HF) or DHF (dilute hydrofluoric acid).

Since the silicon oxide films 11 and 16 have a higher density than thesacrificial film 13 and therefore have a lower etching rate than thesacrificial film 13. Hence, it is possible to obtain a selection ratiobetween the silicon oxide films 11 and 16 and the sacrificial film 13.

Next, the resist film 18 is removed by ashing and wet etching.

As shown in FIG. 8, the silicon oxide film 20 is formed by a plasma CVDmethod. Since the plasma CVD method is a deposition method which haspoor embedding properties, the silicon oxide film 20 is not embedded inthe region from which the sacrificial film 13 has been removed, and theempty portions can be used as air gaps 19.

The semiconductor storage device formed in this way thus has air gaps 19between the word lines WL, and at the sidewall portion on the selectiontransistor ST side of the word line WL1 adjacent to the selectiontransistors ST.

With this arrangement, it is possible to reduce the parasiticcapacitance generated between the word lines and increase the operatingspeed. Further, since the silicon oxide film rather than a nitride filmis used as the sacrificial film for forming the spacers and air gaps, itis possible to suppress the generation of hot carriers and degradationof the tunnel oxide film and thereby obtain a highly reliablesemiconductor storage device.

Here, it is important to note that a distance between the word lines WL,a film thickness of the silicon oxide film 11 and a film thickness ofthe high-permittivity film 12 should satisfy the following relationship.

$\begin{matrix}{{\frac{d_{A}}{ɛ_{A}} + \frac{2d_{H}}{ɛ_{H}} + \frac{2d_{S}}{ɛ_{S}}} > \frac{d_{A} + {2d_{H}} + {2d_{S}}}{ɛ_{S}}} & \left\lbrack {{Formula}\mspace{14mu} 1} \right\rbrack\end{matrix}$

“ε_(A)”, “ε_(H)”, and “ε_(S)” are the relative permittivities of the airgap (air), the high-permittivity film 12, and the silicon oxide film 11,respectively.

“d_(A)”, “d_(H)”, “d_(S)” are the film thicknesses (widths) of the airgap (air), the high-permittivity film 12 and the silicon oxide film 11,respectively.

The space between the word lines where the air gaps are formed can beapproximated as a space between parallel plates as shown in FIG. 9.Under this assumption, the capacitance C between the word lines is avalue which satisfies the following formula. Note that “S” denotes thearea of the plates.

$\begin{matrix}{\frac{1}{C} = {\frac{d_{S}}{ɛ_{S}S} + \frac{d_{H}}{ɛ_{H}S} + \frac{d_{A}}{ɛ_{A}S}}} & \left\lbrack {{Formula}\mspace{14mu} 2} \right\rbrack\end{matrix}$

Further, in the case that a silicon oxide film is embedded between theword lines, a capacitance C′ is given by the following formula.

$\begin{matrix}{C^{\prime} = {ɛ_{S}\frac{S}{{2d_{S}} + {2d_{H}} + d_{A}}}} & \left\lbrack {{Formula}\mspace{14mu} 3} \right\rbrack\end{matrix}$

Since C<C′, Formula 1 can be obtained. Hence, by setting the filmthicknesses of the silicon oxide film 11 and the high-permittivity film12 to satisfy Formula 1, it is possible to reduce the parasiticcapacitance generated between the word lines WL in comparison to when asilicon oxide film is formed between the word lines WL.

As shown in FIG. 6 and FIG. 7, in the embodiment, a resist film 18 withopenings is formed on the memory cell array portion, and the sacrificialfilms 13 between the word lines WL and on the sidewall portion on theselection transistor ST side of the word line WL1 are removed to formthe air gaps in the resulting portions. However, rather than forming theresist film 18, the sacrificial film 13 existing on the sidewalls of theselection transistors ST may also be removed, as shown in FIG. 10.

By subsequently forming a silicon oxide film 22 using a plasma CVDmethod as shown in FIG. 11, it is possible to form a further air gap 21at the sidewall portions of the selection transistors ST. Since it ispossible to omit one of the lithography processes (FIG. 6) used in theabove-described embodiment, it is then possible to reduce manufacturingcost by a corresponding amount.

The semiconductor storage device according to the embodiment has astack-gate memory cell structure formed with a control gateelectrode/interpoly insulating film/floating gate electrode/tunnel oxidefilm stack. However, the air gap formation method can also be applied toan MONOS structure.

When the air gap formation method according to the embodiment is appliedto an MONOS structure, a semiconductor storage device of the type shownin FIG. 12 and FIG. 13 is obtained. The semiconductor storage deviceshown in FIG. 12 has air gaps 110 between the word lines WL and at asidewall portion on the selection transistor side of the end portionword line WL1. The semiconductor storage device shown in FIG. 13 alsohas air gaps 110 at sidewall portions of the selection transistors ST.Upper portions of the air gaps 110 are closed off by a silicon oxidefilm 106.

Here, the word lines WL include a tunnel oxide film 101, a trap nitridefilm 102, an interpoly insulating film (high-permittivity film) 103, anda control gate electrode 104 which are layered in the stated order. Thecontrol gate electrode 104 may be partially or fully formed from asilicide.

The gate electrode 105 of the selection transistor ST is formed usingthe same processes as the control gate electrode 104. The upper portionof the gate electrode 105 is silicide (partial silicide).

Thus, in the semiconductor storage device with the MONOS structure, theoperation speed is improved in the same way as in the above-describedembodiment and the resulting semiconductor storage device is highlyreliable.

1-5. (canceled)
 6. A semiconductor storage device manufacturing method comprising: forming on a semiconductor substrate a plurality of word lines separated by a predetermined interval, each including a first insulating film, a charge storing layer, a second insulating film and a control gate electrode layered in the stated order, and a selection transistor at each end of each of the plurality of word lines at a location adjacent to a plurality of memory regions; forming a first oxide film so as to cover the word lines, the selection transistors and the semiconductor substrate; forming, on the first oxide film, a high-permittivity film which includes a metal oxide and has a higher permittivity than the first oxide film; forming a second oxide film on the high-permittivity film so as to be embedded in gaps between the word lines; removing the second oxide film, the high-permittivity film and the first oxide film so as to expose a surface of the semiconductor substrate between adjacent selection transistors and a surface of the semiconductor substrate between the selection transistors and the word lines adjacent to the selection transistors, and forming sidewall films made up of the first oxide film, the high-permittivity film and the second oxide film on sidewall portions of the selection transistors and on sidewall portions which are of the word lines adjacent to the selection transistors and oppose the selection transistors; forming a nitride film so as to cover the sidewall films and the semiconductor substrate; forming a third oxide film so as to be embedded between the selection transistors and between the selection transistors and the word line adjacent to the selection transistors; removing the third oxide film and the nitride film so as to expose upper surfaces of the control gate electrodes and an upper surface of the second oxide film; removing the second oxide film; and forming a fourth oxide film so as to cover an upper portion of regions from which the second oxide film has been removed.
 7. The semiconductor storage device manufacturing method according to claim 6, wherein the first oxide film is formed at a higher temperature than the second oxide film.
 8. The semiconductor storage device manufacturing method according to claim 6, wherein the second oxide film is formed using a CVD (Chemical Vapor Deposition) method, and the third oxide film is formed using a high-density plasma CVD method.
 9. The semiconductor storage device manufacturing method according to claim 6, wherein the fourth oxide film is formed using a plasma CVD method.
 10. The semiconductor storage device manufacturing method according to claim 6, wherein the second oxide film is removed using wet etching for which the first oxide film and the third oxide film have lower etching rates than the second oxide film. 